Electronic device and method of manufacturing the same

ABSTRACT

The present disclosure provides an electronic device and a method of manufacturing the same. The electronic device includes a multilayer component, at least one contact pad, a passivation layer, a dielectric layer, and a metallic layer. The contact pad is disposed on the multilayer component, the passivation layer covers the multilayer component and the contact pad, and the dielectric layer is disposed on the passivation layer. The metallic layer penetrates through the dielectric layer and the passivation layer and is connected to the contact pad, and the metallic layer discretely tapers at positions of decreasing distance from the contact pad.

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims the priority benefit of U.S. provisional patentapplication No. 62/773,823, filed on Nov. 30, 2018. The entirety of theabove-mentioned patent application is hereby incorporated by referenceherein and made a part of this specification.

TECHNICAL FIELD

The present disclosure relates to an electronic device and a method ofmanufacturing the same, and more particularly, to an electronic devicewith void-free vias and a method of manufacturing the same.

DISCUSSION OF THE BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. In the course of the IC evolution, functional density hasgenerally increased while geometry size has decreased. This scaling-downprocess generally provides benefits by increasing production efficiencyand lowering associated costs. Such scaling down has also increased thecomplexity of processing and manufacturing ICs and, for these advancesto be realized, similar developments in IC manufacturing are needed.

For example, as the semiconductor industry has progressed into nanometertechnology process nodes in pursuit of higher device density, higherperformance, and lower costs, challenges in both fabrication and designhave resulted in the development of multilayer devices. The multilayerdevices may include a plurality of interlayer dielectric layers (ILDs),one or more wiring layers sunk into the interlayer dielectric layers,and one or more vias interposed between two wiring layers. However, asthe scaling down continues, it becomes more difficult to form void-freevias due to poor step coverage of contact holes having a high aspectratio.

This Discussion of the Background section is provided for backgroundinformation only. The statements in this Discussion of the Backgroundare not an admission that the subject matter disclosed in thisDiscussion of the Background section constitute prior art to the presentdisclosure, and no part of this Discussion of the Background section maybe used as an admission that any part of this application, includingthis Discussion of the Background section, constitutes prior art to thepresent disclosure.

SUMMARY

One aspect of the present disclosure provides an electronic device. Theelectronic device includes a multilayer component, at least one contactpad, a passivation layer, a dielectric layer, and a metallic layer. Thecontact pad is disposed on the multilayer component. The passivationlayer covers the multilayer component and the contact pad. Thedielectric layer is disposed on the passivation layer. The metalliclayer penetrates through the dielectric layer and the passivation layer.The metallic layer is connected to the contact pad and discretely tapersat positions of decreasing distance from the contact pad.

In some embodiments, the metallic layer includes a first plug segmentand a second plug segment; the first plug segment is disposed in thepassivation layer and in contact with the contact pad, the second plugsegment is disposed in the dielectric layer and connected to the firstplug segment, and the first plug segment has a first width less than asecond width of the second plug segment.

In some embodiments, the first width is in a range between 1.0 and 2.5μm, and the second width is not less than 5.0 μm.

In some embodiments, the metallic layer further includes a pad segmentdisposed on the dielectric layer and connected to the second plugsegment.

In some embodiments, the metallic layer is a conformal layer.

In some embodiments, the first plug segment, the second plug segment,and the pad segment are integrally formed.

In some embodiments, the passivation layer includes an underlying layerand an overlying layer; the underlying layer is disposed on themultilayer component and the contact pad, and the overlying layer isdisposed between the underlying layer and the dielectric layer.

In some embodiments, at least one of the underlying layer and theoverlying layer has a thickness in a range between 0.8 and 1.0 μm, anddielectric layer has a thickness in a range between 4.0 and 6.0 μm.

In some embodiments, sidewalls of the dielectric layer and the overlyinglayer interfaced with the metallic layer are discontinuous.

In some embodiments, a sidewall of the underlying layer interfaced withthe metallic layer is continuous with the sidewall of the overlyinglayer.

Another aspect of the present disclosure provides a method ofmanufacturing an electronic device. The method includes steps ofproviding a multilayer component; forming at least one contact pad onthe multilayer component; depositing a passivation layer on themultilayer component and the contact pad; creating at least one firsthole in the passivation layer to expose the contact pad; depositing adielectric layer on the passivation layer and into the first hole;removing a portion of the dielectric layer to uncover the contact padand create at least one second hole in the dielectric layer, wherein aportion of a top surface of the passivation layer is exposed through thesecond hole; and depositing a metallic layer on the contact pad and thedielectric layer.

In some embodiments, the second hole communicates with the first hole.

In some embodiments, the method further includes a step of conformallydepositing a diffusion barrier layer on the dielectric layer and intothe second hole and the first hole.

In some embodiments, apertures of the first hole and the second holegradually increase at positions of increasing distance from the contactpad.

In some embodiments, the aperture of the first hole is in a rangebetween 1.0 and 2.5 μm, and the aperture of the second hole is in arange between 8.0 and 10.0 μm.

In some embodiments, the depositing of the passivation layer includessteps of depositing an underlying layer to cover the multilayercomponent, and depositing an overlying layer on the underlying layer.

With the above-mentioned configurations of the electronic device, thestep coverage of the metallic layer is improved since aspect ratios of aspace, constituted of the first hole and the second hole, for fillingthe metallic layer discretely changes. Thus, the problems of poor stepcoverage of the metallic layer are avoided, and a good ohmic contact issecured.

The foregoing has outlined rather broadly the features and technicaladvantages of the present disclosure in order that the detaileddescription of the disclosure that follows may be better understood.Additional features and technical advantages of the disclosure aredescribed hereinafter, and form the subject of the claims of thedisclosure. It should be appreciated by those skilled in the art thatthe concepts and specific embodiments disclosed may be utilized as abasis for modifying or designing other structures, or processes, forcarrying out the purposes of the present disclosure. It should also berealized by those skilled in the art that such equivalent constructionsdo not depart from the spirit or scope of the disclosure as set forth inthe appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present disclosure may be derivedby referring to the detailed description and claims. The disclosureshould also be understood to be coupled to the figures' referencenumbers, which refer to similar elements throughout the description.

FIG. 1 illustrates a cross-sectional view of an electronic device inaccordance with some embodiments of the present disclosure.

FIG. 2 is a flow diagram illustrating a method of manufacturingelectronic devices in accordance with some embodiments of the presentdisclosure.

FIGS. 3 through 20 illustrate cross-sectional views of intermediatestages in the formation of electronic devices in accordance with someembodiments of the present disclosure.

DETAILED DESCRIPTION

Embodiments, or examples, of the disclosure illustrated in the drawingsare now described using specific language. It shall be understood thatno limitation of the scope of the disclosure is hereby intended. Anyalteration or modification of the described embodiments, and any furtherapplications of principles described in this document, are to beconsidered as normally occurring to one of ordinary skill in the art towhich the disclosure relates. Reference numerals may be repeatedthroughout the embodiments, but this does not necessarily mean thatfeature(s) of one embodiment apply to another embodiment, even if theyshare the same reference numeral.

It shall be understood that, although the terms first, second, third,etc. may be used herein to describe various elements, components,regions, layers or sections, these elements, components, regions, layersor sections are not limited by these terms. Rather, these terms aremerely used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the present inventive concept.

The terminology used herein is for the purpose of describing particularexample embodiments only and is not intended to be limited to thepresent inventive concept. As used herein, the singular forms “a,” “an”and “the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. It shall be further understood thatthe terms “comprises” and “comprising,” when used in this specification,point out the presence of stated features, integers, steps, operations,elements, or components, but do not preclude the presence or addition ofone or more other features, integers, steps, operations, elements,components, or groups thereof.

FIG. 1 is a cross-sectional view of an electronic device 10 inaccordance with some embodiments of the present disclosure. Referring toFIG. 1, in some embodiments, the electronic device 10 includes amultilayer component 110, one or more contact pads 120 disposed on themultilayer component 110, a passivation layer 130 covering themultilayer component 110 and the contact pads 120, a dielectric layer140 disposed on the passivation layer 130, and a metallic layer 150penetrating through the dielectric layer 140 and the passivation layer130 and connected to the contact pads 120. In some embodiments, a widthof the metallic layer 150 discretely tapers, such that sidewalls 1502 ofthe metallic layer 150 are discontinuous from a top surface 1504 of themetallic layer 150 to a bottom surface 1506 opposite to the top surface1504, wherein the bottom surface 1506 is in contact with the contact pad120.

In some embodiments, the contact pads 120 may have a square shape whenviewed in a plan view. In some embodiments, the contact pads 120 withsmallest dimension have a length L substantially equal to 10.0 μm. Insome embodiments, the contact pads 120 are made of conductive material,such as copper, copper alloys, aluminum, or a combination thereof.

In some embodiments, the passivation layer 130 is conformally disposedon the multilayer component 110 and the contact pads 120. In someembodiments, the passivation layer 130 includes an underlying layer 132in contact with the multilayer component 110 and the contact pad 120 andan overlying layer 134 covering the underlying layer 132. In someembodiments, the underlying layer 132 has a first thickness T1 and theoverlying layer 134 has a second thickness T2 substantially equal to orless than the first thickness T1. In some embodiments, the firstthickness T1 may be, for example, in a range between 0.5 and 1.5micrometers (μm), such as about 1.0 μm. In some embodiments, the secondthickness T2 is about 0.8 μm. In some embodiments, the underlying layer132 includes oxide, and the overlying layer 134 includes nitride.

In some embodiments, the dielectric layer 140 is a conformal layer. Insome embodiments, the dielectric layer 140 has a thickness T greaterthan the first thickness T1. In some embodiments, the thickness T maybe, for example, in a range between 4.0 and 6.0 μm, such as about 5.5μm. In some embodiments, the dielectric layer 140 includes nitride.

In some embodiments, the metallic layer 150 includes one or more firstplug segments 152 disposed in the passivation layer 130 and one or moresecond plug segments 154 disposed in the dielectric layer 140 andconnected to the first plug segments 152, respectively. In someembodiments, the first plug segments 152 are respectively in contactwith the contact pads 120. In some embodiments, the first plug segment152 has a first width W1 (e.g., a top or a maximum width), and thesecond plug segment 154 has a second width W2 greater than the firstwidth W1. In some embodiments, the first width W1 and the second widthgradually increase at positions of increasing distance from the contactpads 120. In some embodiments, the first width W1 may be, for example,in a range between 1.0 and 2.5 μm, such as about 2.4 μm. In someembodiments, the second width W2 may be not less than 5.0 μm. In someembodiments, the second width W2 is in a range between 8.0 and 10.0 μm.

In some embodiments, the metallic layer 150 further includes one or morepad segments 156 disposed on the dielectric layer 140 and respectivelyconnected to the second plug segment 154. In some embodiments, the firstplug segment 152, the second plug segment 154, and the pad segment 156may be integrally formed. In some embodiments, the metallic layer 150 isa substantially conformal layer.

FIG. 2 is a flow diagram illustrating a method 200 of manufacturingelectronic devices 10/10A in accordance with some embodiments of thepresent disclosure. FIGS. 3 to 20 are schematic diagrams illustratingvarious fabrication stages constructed according to the method 200 ofmanufacturing the electronic devices 10/10A in accordance with someembodiments of the present disclosure. The stages shown in FIGS. 3 to 20are also illustrated schematically in the flow diagram in FIG. 2. In thesubsequent discussion, the fabrication stages shown in FIGS. 3 to 20 arediscussed in reference to the process steps in FIG. 2.

Referring to FIG. 3, a multilayer component 110 is provided according toa step 202 in FIG. 2. In some embodiments, the multilayer component 110may include a main component 1102 including one or more features, suchas transistors, resistors, capacitors, diodes, etc. In some embodiments,the multilayer component 110 may further include an interconnectionstructure, including alternating stacking of wiring layers M1, M2 andvias V1, V2, V3, disposed over the main component 1102, and one or moreinterlayer dielectrics ILD1, ILD2, ILD3 encircling the wiring layers M1,M2 and the vias V1, V2, V3.

Next, a blanket conductive layer 210 is deposed on the multilayercomponent 110 according to a step 204 in FIG. 2. In some embodiments,the blanket conductive layer 210 may include aluminum, aluminum alloys,copper, copper alloys, titanium, tungsten, polysilicon, or a combinationthereof. In some embodiments, the blanket conductive layer 210 may beformed by a variety of techniques, e.g., physical vapor deposition(PVD), chemical vapor deposition (CVD), sputtering, and the like.

Referring to FIGS. 3 and 4, in some embodiments, the blanket conductivelayer 210 is next patterned by an etching process that produces one ormore contact pads 120 according to a step 206 in FIG. 2. In someembodiments, the contact pads 120 are formed by steps including (1)providing a mask layer 220 on the blanket conductive layer 210, (2)performing a photolithography process to define a pattern required toform the contact pads 120, (3) performing an etching process to removeportions of the blanket conductive layer 210 exposed through the masklayer 220, and (4) removing the mask layer 220.

Referring to FIG. 5, in some embodiments, an underlying layer 132 isdeposited to cover the multilayer component 110 and the contact pads 120according to a step 208 in FIG. 2. In some embodiments, the underlyinglayer 132 is a substantially conformal layer. In some embodiments, theunderlying layer 132 may include silicon dioxide (SiO₂). In someembodiments, the underlying layer 132 is formed, for example, using aCVD process or a spin coating process.

Referring to FIG. 6, in some embodiments, an overlying layer 134 isdeposited on the underlying layer 132 according to a step 210 in FIG. 2.In some embodiments, the overlying layer 134 includes silicon nitride(Si₃N₄). In some embodiments, the overlying layer 134 is a substantiallyconformal layer. In some embodiments, the overlying layer 134 is formed,for example, using a CVD process.

Referring to FIG. 7, in some embodiments, a first photoresist layer 230is coated on the overlying layer 134 according to a step 212 in FIG. 2.In some embodiments, the first photoresist layer 230 fully covers theoverlying layer 134. The first photoresist layer 230 is then patternedto define one or more regions where the overlying layer 134 and theunderlying layer 132 are to be subsequently etched. In some embodiments,the first photoresist layer 230 is patterned by steps including (1)exposing the first photoresist layer 230 to a pattern (not shown), (2)performing a post-exposure back process, and (3) developing the firstphotoresist layer 230, thereby forming a first photoresist pattern 232having one or more first openings 234, as shown in FIG. 8. In someembodiments, a portion of the overlying layer 134 to be subsequentlyetched is exposed through the first openings 234. In some embodiments,the first openings 234 are directly over the contact pads 120.

Referring to FIG. 9, in some embodiments, a first etching process isperformed to etch the overlying layer 134 and the underlying layer 132and thus create one or more first holes 240 according to a step 214 inFIG. 2. In some embodiments, portions of the contact pads 120 areexposed through the first holes 240. In some embodiments, the firstetching process includes a wet etching process, a dry etching process,or a combination thereof.

Referring to FIG. 10, after the first etching process, the firstphotoresist pattern 232 is removed according to a step 216 in FIG. 2. Insome embodiments, an ashing process or a wet strip process may be usedto remove the first photoresist pattern 232, wherein the wet stripprocess may chemically alter the first photoresist pattern 232 so thatit no longer adheres to the overlying layer 134. In some embodiments,the first holes 240 have a first aperture A1 (e.g., a top or a maximumaperture), which is less than a length L of the contact pad 120. In someembodiments, the first aperture A1 is, for example, in a range between1.0 and 2.5 μm. In some embodiments, the first aperture A1 graduallyincreases at positions of increasing distance from the contact pads 120.

Referring to FIG. 11, in some embodiments, a dielectric layer 140 isconformally deposited on the overlying layer 134 and into the firstholes 240 according to a step 218 in FIG. 2. In some embodiments, thedielectric layer 140 extends along a top surface 1342 of the overlyinglayer 134 and into the first holes 240. In some embodiments, thedielectric layer 140 includes silicon dioxide. In some embodiments, thedielectric layer 140 is formed, for example, using a CVD process.

Referring to FIGS. 12 and 13, in some embodiments, a second photoresistlayer 250 is coated on the dielectric layer 140 according to a step 220in FIG. 2. In some embodiments, the second photoresist layer 250 fullycovers the dielectric layer 140. The second photoresist layer 250 isthen patterned to define one or more regions where the dielectric layer140 is to be subsequently etched. In some embodiments, the secondphotoresist layer 250 is patterned by steps including (1) exposing thesecond photoresist layer 230 to a pattern (not shown), (2) performing apost-exposure back process, and (3) developing the second photoresistlayer 250, thereby forming a second photoresist pattern 252 having oneor more second openings 254 over the contact pads 120. In someembodiments, a portion of the dielectric layer 140 to be subsequentlyetched is exposed through the second openings 254. In some embodiments,the first etching process includes a wet etching process, a dry etchingprocess, or a combination thereof.

Referring to FIG. 14, in some embodiments, a second etching process isperformed to uncover the contact pads 120 according to a step 222 inFIG. 2. In some embodiments, the contact pads 120 are uncovered byselectively removing a portion of the dielectric layer 140 exposedthrough the second photoresist pattern 252; accordingly, the first holes240 are reopened, and one or more second holes 260 are formedpenetrating through the dielectric layer 140 and communicating with thefirst holes 240, respectively. In some embodiments, the second etchingprocess includes a wet etching process, a dry etching process, or acombination thereof.

Referring to FIG. 15, after the second etching process, the secondphotoresist pattern 252 is removed according to a step 224 in FIG. 2. Insome embodiments, an ashing process or a wet strip process may be usedto remove the second photoresist pattern 252, wherein the wet stripprocess may chemically alter the second photoresist pattern 252 so thatit no longer adheres to the dielectric layer 140. In some embodiments,the second holes 260 have a second aperture A2 greater than the firstaperture A1. In some embodiments, the second aperture A2 is in a rangebetween 8.0 and 10.0 μm. In some embodiments, the second aperture A2gradually increases at positions of increasing distance from the contactpads 120. In some embodiments, the remaining underlying layer 132 has asidewall 1322, the remaining overlying layer 134 has a sidewall 1342continuous with the sidewall 1322, and the remaining dielectric layer140 has a sidewall 1402 discontinuous with the sidewall 1342.

Referring to FIG. 16, in some embodiments, a metallic layer 150 isconformally deposited on the dielectric layer 140 and into the firstholes 240 and the second holes 260 according to a step 226 in FIG. 2. Insome embodiments, the metallic layer 150 is physically connected to thecontact pads 120. In some embodiments, the metallic layer 150 includescopper or aluminum. In some embodiments, the metallic layer 150 isformed using a physical vapor deposition (PVD) process or a sputteringprocess.

In the present disclosure, a space (or “contact hole”) for filling themetallic layer 150 is constituted of the first hole 240 having the firstaperture A1 and the second hole 260 having the second aperture A2greater than the first aperture A1. Thus, the problems of poor stepcoverage of the metallic layer 150 are avoided, and a good ohmic contactis secured.

Referring to FIG. 17, in some embodiments, a patterning process isperformed to define circuit routes on the metallic layer 150 accordingto a step 228 in FIG. 2. Accordingly, the electronic device 10 iscompletely formed. In some embodiments, the circuit routes mayfacilitate electrical coupling between the electronic device 10 andexternal devices.

FIGS. 18 through 20 illustrate the formation of an electronic device 10Ain accordance with alternative embodiments. Unless specified otherwise,the materials and formation methods of the components in theseembodiments are essentially the same as those of the like components,which are denoted by like reference numerals in the embodiments shown inFIGS. 3 through 17. The details of the like components shown in FIGS. 18through 20 may thus be found in the discussion of the embodiments shownin FIGS. 3 through 17.

Referring to FIG. 18, in some embodiments, the electronic device 10Afurther includes a diffusion barrier layer 160 disposed at interfacesbetween the dielectric layer 140 and the metallic layer 150, between theoverlying layer 134 and the metallic layer 150, between the underlyinglayer 132 and the metallic layer 150, and between the contact pads 120and the metallic layer 150. The formation process of the electronicdevice 10A is similar to the process for forming the electronic device10, except the formation of the electronic device 10A is started afterthe second holes 260 are formed and the first holes 240 are reopened,and before the circuit routes are defined. For example, FIGS. 19 and 20illustrate cross-sectional views of intermediate stages in the formationof the electronic device 10A shown in FIG. 18.

Referring to FIG. 19, in some embodiments, after formation of the secondholes 260, a diffusion barrier layer 160 is deposited on the dielectriclayer 140 and into the second holes 260 and the first holes 240according to a step 225 in FIG. 3. In some embodiments, the diffusionbarrier layer 160 is in contact with the contact pads 120. In someembodiments, the diffusion barrier layer 160 is a substantiallyconformal layer. In some embodiments, the diffusion barrier layer 160may improve adhesion of a metallic material 150, which is to be formedduring a subsequent process, to the dielectric layer 140. In someembodiments, refractory metals, refractory metal nitrides, refractorymetal silicon nitrides and combinations thereof are typically used forthe diffusion barrier layer 160. In some embodiments, the diffusionbarrier layer 160 may include titanium (Ti), titanium nitride (TiN),tantalum (Ta), tantalum nitride (TaN), titanium silicon nitride (TiSN),tantalum silicon nitride (TaSiN), or the like. In some embodiments, thediffusion barrier layer 160 is formed using a PVD process or an atomiclayer deposition process, for example.

Referring to FIG. 20, in some embodiments, the metallic layer 150 isdeposited on the diffusion barrier layer 160 according to a step 226 inFIG. 2. In some embodiments, the metallic layer 150 is a substantiallyconformal layer. The process steps and the material for forming themetallic layer 150 may be found by referring to the embodiments shown inFIG. 16. Next, as shown in FIG. 18, circuit routes are formed in themetallic layer 150, and hence the electronic device 10A is completelyformed.

In conclusion, with the configuration of the electronic device 10/10A,the step coverage of the metallic layer 150 is improved since aspectratios of a space, constituted of the first hole 240 and the second hole260, for filling the metallic layer 150 discretely changes. Thus, theproblems of poor step coverage of the metallic layer 150 are avoided,and a good ohmic contact is secured.

One aspect of the present disclosure provides an electronic device. Theelectronic device includes a multilayer component, at least one contactpad, a passivation layer, a dielectric layer, and a metallic layer. Thecontact pad is disposed on the multilayer component, the passivationlayer covers the multilayer component and the contact pad, and thedielectric layer is disposed on the passivation layer. The metalliclayer penetrates through the dielectric layer and the passivation layerand is connected to the contact pad. The metallic layer discretelytapers at positions of decreasing distance from the contact pad.

One aspect of the present disclosure provides a method of manufacturingan electronic device. The method includes steps of providing amultilayer component; forming at least one contact pad on the multilayercomponent; depositing a passivation layer on the multilayer componentand the contact pad; creating at least one first hole in the passivationlayer to expose the contact pad; depositing a dielectric layer on thepassivation layer and into the first hole; removing a portion of thedielectric layer to uncover the contact pad and create at least onesecond hole in the dielectric layer, wherein a portion of a top surfaceof the passivation layer is exposed through the second hole, anddepositing a metallic layer on the contact pad and the dielectric layer.

Although the present disclosure and its advantages have been describedin detail, it should be understood that various changes, substitutionsand alterations can be made herein without departing from the spirit andscope of the disclosure as defined by the appended claims. For example,many of the processes discussed above can be implemented in differentmethodologies and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, and composition of matter, means, methods and stepsdescribed in the specification. As one of ordinary skill in the art willreadily appreciate from the present disclosure, processes, machines,manufacture, compositions of matter, means, methods, or steps, presentlyexisting or later to be developed, that perform substantially the samefunction or achieve substantially the same result as the correspondingembodiments described herein may be utilized according to the presentdisclosure. Accordingly, the appended claims are intended to includewithin their scope such processes, machines, manufacture, compositionsof matter, means, methods, or steps.

1. An electronic device, comprising: a multilayer component; at leastone contact pad disposed on the multilayer component; a passivationlayer covering the multilayer component and the contact pad; adielectric layer disposed on the passivation layer; and a metallic layerpenetrating through the dielectric layer and the passivation layer andconnected to the contact pad, wherein the metallic layer comprises afirst plug segment disposed in the passivation layer and in contact withthe contact pad; wherein the first plug segment of the metallic layerdiscretely tapers at positions of decreasing distance from the contactpad.
 2. The electronic device of claim 1, wherein the metallic layercomprises: a second plug segment disposed in the dielectric layer andconnected to the first plug segment, wherein the first plug segment hasa first width less than a second width of the second plug segment,wherein the second plug segment of the metallic layer discretely tapersat positions of decreasing distance from the contact pad.
 3. Theelectronic device of claim 2, wherein the first width is in a rangebetween 1.0 and 2.5 μm, and the second width is not less than 5.0 μm. 4.The electronic device of claim 2, wherein the metallic layer furthercomprises a pad segment disposed on the dielectric layer and connectedto the second plug segment.
 5. The electronic device of claim 4, whereinthe metallic layer is a conformal layer.
 6. The electronic device ofclaim 4, wherein the first plug segment, the second plug segment, andthe pad segment are integrally formed.
 7. The electronic device of claim1, wherein the passivation layer comprises: an underlying layer disposedon the multilayer component and the contact pad; and an overlying layerdisposed between the underlying layer and the dielectric layer.
 8. Theelectronic device of claim 7, wherein at least one of the underlyinglayer and the overlying layer has a thickness in a range between 0.8 and1.0 μm, and the dielectric layer has a thickness in a range between 4.0and 6.0 μm.
 9. The electronic device of claim 7, wherein sidewalls ofthe dielectric layer and the overlying layer interfaced with themetallic layer are discontinuous.
 10. The electronic device of claim 9,wherein a sidewall of the underlying layer interfaced with the metalliclayer is continuous with the sidewall of the overlying layer.
 11. Amethod of manufacturing an electronic device, comprising: providing amultilayer component; forming at least one contact pad on the multilayercomponent; depositing a passivation layer on the multilayer componentand the contact pad; creating at least one first hole in the passivationlayer to expose the contact pad, wherein the first hole includes anaperture gradually increasing at positions of increasing distance fromthe contact pad; depositing a dielectric layer on the passivation layerand into the first hole; removing a portion of the dielectric layer touncover the contact pad and create at least one second hole in thedielectric layer, wherein a portion of a top surface of the passivationlayer is exposed through the second hole; and depositing a metalliclayer on the contact pad and the dielectric layer.
 12. The method ofclaim 11, wherein the second hole communicates with the first hole. 13.The method of claim 12, further comprising conformally depositing adiffusion barrier layer on dielectric layer and into the second hole andthe first hole.
 14. The method of claim 11, wherein the second holeincludes an aperture gradually increasing at positions of increasingdistance from the contact pad.
 15. The method of claim 14, wherein theaperture of the first hole is in a range between 1.0 and 2.5 μm, and theaperture of the second hole is in a range between 8.0 and 10.0 μm. 16.The method of claim 11, wherein the depositing of the passivation layercomprises: depositing an underlying layer to cover the multilayercomponent; and depositing an overlying layer on the underlying layer.